1. Field of the Invention
The present invention relates to a test circuit, and more particularly, to a test circuit including a TAP (Test Access Port) controller defined in IEEE1149.
2. Description of Related Art
A circuit size of a semiconductor device has recently become larger and larger, and a number of terminals performing test on the semiconductor device has been increasing. A package of the semiconductor device becomes larger and miniaturization of the semiconductor device is difficult as the number of terminals is increased. It is therefore required to reduce the number of terminals. In order to achieve this, IEEE (Institute of Electrical and Electronics Engineers) has defined IEEE1149. With IEEE1149.1, which is one of IEEE1149, it is possible to perform test of the semiconductor device using five terminals and a TAP controller. The five terminals are called a TDI terminal, a TRST terminal, a TCK terminal, a TMS terminal, and a TDO terminal. In the following description, a set of TDI terminal, TRST terminal, TCK terminal, TMS terminal, and TDO terminal is called test terminal group. The TAP controller includes a state machine changing internal state based on TMS signal input from the TMS terminal and controls test target block based on commands input from the TDI terminal.
As the circuit size is increased, a plurality of TAP controllers are used according to a number of test target blocks. However if the plurality of TAP controllers are directly implemented, a plurality of test terminal groups need to be provided according to the number of TAP controllers, which means the number of terminals is increased. In order to overcome this problem, Japanese Unexamined Patent Application Publication No. 2004-164367 (hereinafter referred to as related art 1) discloses a technique preventing the number of terminals from being increased even when the plurality of TAP controllers are implemented.
FIG. 24 shows a block diagram of a semiconductor device 1000 disclosed in the related art 1. As shown in FIG. 24, the semiconductor device 1000 includes TAP controllers 1200 and 1300, and CPUs 1220 and 1320 connected to the TAP controllers 1200 and 1300 through debug executing units. In the semiconductor device 1000, a set of test terminal group is included in each of the two TAP controllers. The semiconductor device 1000 further includes a selecting circuit 1100 for selecting connection path connecting the set of test terminal group and the TAP controller 1200 and the TAP controller 1300.
More specifically, the selecting circuit 1100 includes a TAP controller 1110 and a register 1101. The TAP controller 1110 sets the value stored in the register 1101 according to instruction code input from the TDI terminal. The selecting circuit 1100 then selects the connection path connecting the test terminal group and the TAP controller 1200 and the TAP controller 1300 according to the value stored in the register 1101.
The related art 1 also shows an example where the TAP controller is not included in the selecting circuit 1100. In this case, an input terminal of control signal to the selecting circuit 1100 is provided in addition to a set of test terminal group.
Another example of a control method of the plurality of TAP controllers is shown in Japanese Patent Translation Publication No. 2005-527918 (hereinafter referred to as related art 2) and Japanese Unexamined Patent Application Publication No. 2002-373086 (hereinafter referred to as related art 3). In the control method disclosed in the related art 2, the plurality of TAP controllers are controlled by adding the control circuit or other terminal than the test terminal group. In the control method disclosed in the related art 3 as well, the plurality of TAP controllers are controlled by adding the selecting circuit and controlling the selecting circuit according to signals from the test terminal group. The related art controlling the plurality of TAP controllers is disclosed in Japanese Unexamined Patent Application Publication No. 10-115668 (hereinafter referred to as related art 4). In the related art 4, the plurality of TAP controllers are controlled through a TAP link module (hereinafter referred to as control circuit). U.S. Pat. Nos. 6,324,662, 6,711,707, and 7,213,171 are U.S. patents corresponding to Japanese Unexamined Patent Application Publication No. 10-115668.
However, we have now discovered that there are problems in the techniques disclosed in related art 1 to related art 4. The instruction code that is input to the selecting circuit or the control circuit that is added does not comply with a standard specification of IEEE1149.1. Therefore, incompatibility of the instruction code may be raised among semiconductor devices when the circuits are implemented on the substrate with other semiconductor devices, which causes malfunction of behavior of the system.
Further, in related art 2 to related art 4, operation procedure of the selecting circuit or the control circuit does not comply with the standard specification of IEEE1149.1. Therefore, incompatibility of the operation procedure may be raised among semiconductor devices when the circuits are implemented on the board with other semiconductor devices, which causes malfunction of behavior of the system.